通知公告
学术报告信息
一、报告题目：Polar Codes and Efficient Architectures forSuccessive Cancellation Polar Decoder
二、报告时间：2013年12月13日（周五）下午14:30
三、报告地点：斛兵楼一楼学术报告厅
四、主办单位：电子科学与应用物理学院
五、报告内容简介：
Polar codes have recently emerged as one of the most favorable capacity-achieving error correction codes due to their low encoding and decoding complexity. However, because of the large code length required by practical applications, the few existing successive cancellation (SC) decoder implementations still suffer from not only high hardware cost but also long decoding latency. In this talk, a data-flow graph (DFG) for the SC decoder is derived. A complete hardware architecture is first derived for the conventional tree SC decoder and thefeedback partis presented next.Pre-computation look-aheadtechnique is exploited to reduce the achievable minimum decoding latency. Sub-structure sharing is used to design amerged processing element(PE) for higher hardware utilization. In order to meet throughput requirements for a diverse set of application scenarios, a systematic approach to construct different overlapped SC polar decoder architectures is also presented. Compared with a conventionalN-bit tree SC decoder, the proposed overlapped architectures can achieve as high as (N-1) times speedup with only (N∙log2N)/2mergedPEs. The proposed pre-computation approach leads to a 50% reduction in latency forN> 27, and 40% reduction forN≤ 27.
If I have more time, I will present the first systematic approach to formally derive the simplified successive cancellation (SSC) decoding latency for any given polar code, and the method to derive the SSC polar decoder architecture for any specific code. Compared with their SC decoder counterparts, the proposed SSC and pre-computation SSC polar decoders can save up to 39.6% decoding latency with the same hardware cost.